This invention is in the field of microcomputers and microprocessors. More specifically, it is in the area of interfacing peripheral devices and/or other processors to the microcomputer or microprocessor.
A rapidly accelerating trend in the electronics industry is the increased demand for fast computational abilities. To try to meet this demand, the industry has introduced families of digital signal processing microcomputers, high-speed conventional microprocessors, and other fast processors. It is becoming apparent that one of the major bottlenecks in pushing for still higher speed is getting data in and out of the processor itself.
The industry has tried numerous approaches to solve this problem when memory access is the issue. Techniques such as pipelining, caching, etc. have been successfully employed. However one area that has not been adequately addressed is that of I/O to remote (i.e. off-chip) devices.
It is an object of the present invention to avoid creating an I/O bottleneck.
The vast majority of systems have a hardwired type of handshake between the microprocessor/microcomputer and the peripheral device. This handshake generally requires the processor to wait until the other device is ready during a read or a write operation. This in turn usually means that the reads and/or writes must be synchronous with the system clock.
It is an object of the present invention to allow a handshaking protocol, without forcing the processor to wait for the other device.
It is also an object of the invention to allow asynchronous reads and writes.
However, asynchronous communications are relatively slow. Ideally one would want to have the ability to communicate asynchronously with slow peripherals, but synchronously with fast ones. The normal disadvantage to this is the vastly increased number of I/O pins required.
It is an object of the invention to allow both asynchronous and synchronous communications.
It is also an object of the invention to minimize the number of I/O pins required.
It is a further object of the invention to allow rapid changes between communicating with slow peripherals and with fast peripherals.
Current I/O interfaces are designed to operated with fixed bus widths. If a processor has a 16 bit data bus, then peripherals are expected to be 16 bits in data width. This limits the number of devices that can be attached. In addition, if a 16 bit processor wishes to communicate with an 8 bit processor, added external logic is required.
It is an object of the invention to allow the processor to communicate with peripheral devices having varying data bus widths.
It is also an object of the invention to allow different processors having different data bus widths to communicate in a simple manner.
It is a further object of the invention to allow interface communications to occur with minimal external logic.
In some cases, it is desirable for the processor to operate in a master mode. This means that all communications occur in response to the processor's initiation. Conversely, there are situations where the processor should act as a slave to another system master. In the past, switches of this type required substantial setup overhead both in hardware and in software.
It is an object of the invention to allow the processor to to function in either a master or a slave environment.
It is also an object of the invention to allow rapid mode changes.
Technological advances in microprocessors/microcomputers have limited the market lifespan of any product. New processors are introduced that outdate the prior generation. To take advantage of the new features, a redesign of the entire product is frequently required.
It is an object of the invention to allow a product to be upgraded to a new processor generation without redesigning the product.
The processor vendor is also benefited. In the past, new generation processor would outdate his old line, making the line unprofitable to maintain. However, to support his customers, the vendor would have to keep stocking the old processor.
It is an object of the invention to allow the vendor to supply as a replacement part for an old generation product, a new generation part.
The vendor has another problem with new generations. Test patterns have been developed to exercise and qualify the old parts. These are highly timing dependent. When a new generation is introduced, the vendor normally has to create a whole new test pattern. This can also lead to difficulties in detecting subtle incompatibilities.
It is an object of the invention to allow the vendor to use the older generation product's test patterns.
These and other objects of the invention are achieved by a multi-mode processor having a plurality of I/O pins comprising:
a data bus coupled to selected ones of said I/O pins;
control lines coupled to other ones of said I/O pins;
said processor having a first communications mode wherein said data bus is selectively coupled to a first I/O port structure and said processor controls the input and output of data over said data bus;
said processor having a second communications mode wherein said data bus is selectively coupled to a second I/O port structure and the input and output of data over said data bus is controlled in response to said control lines; and
said processor being switchable between said first and second communications modes in response to signals received on selected ones of said I/O pins.